In a parallel computer system or a network device having a plurality of access spaces such as a memory space and a communication register space, a method of guaranteeing a plurality of access spaces has been considered. As a method of guaranteeing consistency in combination of a memory space and a communication register space, a method in which writing is performed after waiting for completion of preceding write at the time of synchronization has been known.
FIG. 1 illustrates an example of writing the data body to a memory region and writing a flag to a communication register. For example, a particular bit of an address accessing the communication register is defined as an identification flag for synchronization, and when the flag is asserted, completion of preceding write is waited for. In that case, after waiting for completion of preceding write issued to the memory region at time 0 (wait for a reply at NonPostedWrite), writing of a flag to the communication register is performed at time 3.
In the aforementioned method, as a flag is written at the end (global visibility of the flag comes last inevitably), when the flag is able to be seen on the processor core side, completion of preceding write is guaranteed. Accordingly, it is easy as a method of guaranteeing consistency. Meanwhile, even in the case where a flag is written to a memory, it is possible to perform synchronization by asserting a particular address bit, or it is also possible to have a flag for synchronization in an address translation mechanism such as TLB (Translation Lookaside Buffer).
Further, as another method of guaranteeing consistency in combination of a memory space and a communication register space, a method of performing synchronization from the receiving side has been known. For example, FIG. 2 illustrates the case where the data body is written to the memory region and a flag is written to the communication register. In FIG. 2, a synchronization command is issued to each of different spaces. This means that for the synchronization of a memory space, a FENCE command (MFEN) for the memory is issued.
Meanwhile, for the synchronization of a communication register space, a FENCE command (CFEN) for the communication register is issued. In this case, two synchronization commands must be issued.
Patent Literature 1: JP 2010-44599 A
However, the aforementioned method in which writing is performed after waiting for completion of preceding write at the time of synchronization has a problem in that, although easy to implement, while waiting for as completion of the preceding write, there is a free space in the internal bus that is inefficient.
Further, the method of performing synchronization from the receiving side has another problem that as synchronization is performed for each space, visibility from a user is poor, and it takes labor.
As related art, Patent Literature 1 discloses a technology of guaranteeing global visibility of data to be stored in a memory. However, it is not a method of efficiently guaranteeing a plurality of access spaces.